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features description/ordering information PCA8550 nonvolatile 5-bit register with i 2 c interface scps050c ? march 1999 ? revised may 2005 epic? (enhanced-performance implanted cmos) submicron process useful for jumperless configuration of pc motherboard inputs accept voltages to 5.5 v mux out signals are 2.5-v outputs non-muxed out signal is a 3.3-v output minimum of 1000 write cycles minimum of 10 years data retention package options include plastic small-outline (d), shrink small-outline (db), and thin shrink small-outline (pw) packages this 4-bit 1-of-2 multiplexer with i 2 c input interface is designed for 3-v to 3.6-v v cc operation. the PCA8550 is designed to multiplex four bits of data from parallel inputs or from i 2 c input data stored in a nonvolatile register. an additional bit of register output also is provided, which is latched to prevent changes in the output value during the write cycle. the factory default for the contents of the register is all low. these stored values can be read from, or written to, using the i 2 c bus. the ability to control writing to the register is provided by the write protect (wp) input. the override ( override) input forces all the register outputs to a low. this device provides a fast-mode (400 kbit/s) or standard-mode (100 kbit/s) i 2 c serial interface for data input and output. the implementation is as a slave. the device address is specified in the i 2 c interface definition table. both of the i 2 c schmitt-trigger inputs (scl and sda) provide integrated pullup resistors and are 5-v tolerant. the PCA8550 requires a monotonic power-supply ramp at start-up in the region of 1.1 v to 2.5 v. the nonvolatile registers and i 2 c state machine initialize to their default states after this v cc level is passed. the PCA8550 is characterized for operation from 0 c to 70 c. ordering information t a package (1) orderable part number top-side marking tube of 40 PCA8550d soic ? d reel of 2500 PCA8550dr 0 c to 70 c PCA8550 ssop ? db reel of 2000 PCA8550dbr tssop ? pw reel of 2000 PCA8550pwr (1) package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. epic is a trademark of texas instruments. production data information is current as of publication date. copyright ? 1999?2005, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www .ti.com 12 3 4 5 6 7 8 1615 14 13 12 1 1 10 9 i 2 c scl i 2 c sda override mux in amux in b mux in cmux in d gnd v c c wpnon-muxed out mux select mux out a mux out b mux out c mux out d d, db, or pw p ackage (t op view)
PCA8550 nonvolatile 5-bit register with i 2 c interface scps050c ? march 1999 ? revised may 2005 function table inputs outputs mux select override mux out non-muxed out l l l l l h nonvolatile register nonvolatile register h x mux in latched non-muxed out (1) (1) the latched non-muxed out state is the value present on the non-muxed out output at the time the mux select input transitions from the low to the high state. logic diagram (positive logic) 2 www .ti.com 5-bit nonvolatile register i 2 c interface logic address: 1001 1 10 1-bit t ransparent latch 4-bit 1-of-2 multiplexer non-muxedout mux out amux out b mux out c mux out d mux in a scl sda override wp mux in bmux in c mux in d mux select v c c v c c v c c v c c v c c 1 2 15 34 5 6 7 13 1412 1 1 10 9
i 2 c interface absolute maximum ratings (1) PCA8550 nonvolatile 5-bit register with i 2 c interface scps050c ? march 1999 ? revised may 2005 i 2 c communication with this device is initiated by a master sending a start condition, a high-to-low transition on the serial data (sda) input/output while the serial clock (scl) input is high. after the start condition, the device address byte is sent, msb first, including the data-direction bit (r/ w). this device does not respond to the general call address. after receiving the valid address byte, this device responds with an acknowledge, a low on the sda input/output during the high of the acknowledge-related clock pulse. the data byte follows the address acknowledge. if the r/ w bit is high, the data from this device are the values read from the nonvolatile register. if the r/ w bit is low, the data are from the master, to be written into the register. a valid data byte is one in which the three high-order bits are low. the first valid data byte that is received is written into the register, following the stop condition. if an invalid data byte is received, it is acknowledged, but is not written into the register. the data byte is followed by an acknowledge sent from this device. if other data bytes are sent from the master, following the acknowledge, they are ignored by this device. a stop condition, a low-to-high transition on the sda input/output while the scl input is high, is sent by the master. if the wp input is low during the falling edge of the first valid data byte acknowledge on the scl input and the r/ w bit is low, the stop condition causes the i 2 c interface logic to write the data byte value into the nonvolatile register. data are written only if complete bytes are received and acknowledged. writing to the register takes time (t wr ), during which the device does not respond to its slave address. if the wp input is high, the i 2 c interface logic does not write to the register. i 2 c interface definition table bit byte 7 (msb) 6 5 4 3 2 1 0 (lsb) address h l l h h h l r/ w non- data l l l mux out d mux out c mux out b mux out a muxed out over operating free-air temperature range (unless otherwise noted) min max unit v cc supply voltage range ?0.5 6.5 v v i input voltage range (2) ?0.5 6.5 v sda (2) ?0.5 6.5 v o output voltage range mux out outputs (2) ?0.5 2.9 v non-muxed out output (2) (3) ?0.5 v cc + 0.5 i ik input clamp current v i < 0 ?50 ma i ok output clamp current v o < 0 or v o > v cc (3) ?50, +10 ma i iok input/output clamp current v o < 0 ?50 ma i o continuous output current v o = 0 to v cc (3) 15 ma continuous current through v cc or gnd 30 ma d package 113 q ja package thermal impedance (4) db package 131 c/w pw package 149 t stg storage temperature range ?65 85 c (1) stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) the value of v cc is provided in the recommended operating conditions table. (4) the package thermal impedance is calculated in accordance with jesd 51. 3 www .ti.com
recommended operating conditions electrical characteristics nonvolatile storage specifications PCA8550 nonvolatile 5-bit register with i 2 c interface scps050c ? march 1999 ? revised may 2005 min max unit v cc supply voltage 3 3.6 v scl, sda 2.7 4 v ih high-level input voltage v override, mux in, mux select, wp 2 4 scl, sda ?0.5 0.9 v il low-level input voltage v override, mux in, mux select, wp ?0.5 0.8 i oh high-level output current mux out, non-muxed out ?2 ma sda 6 i ol low-level output current ma mux out, non-muxed out 2 d t/ d v input transition rise or fall rate override, mux in, mux select, wp 10 ns/v t a operating free-air temperature 0 70 c over recommended operating free-air temperature range, v cc = 3.3 v 0.3 v (unless otherwise noted) parameter test conditions min max unit v ik input diode clamp voltage i i = ?18 ma ?1.5 v v hys (1) scl, sda 0.19 v i oh = ?100 m a 2 2.625 mux out i oh = ?1 ma 1.7 2.625 v oh v i oh = ?100 m a 2.4 3.6 non-muxed out i oh = ?2 ma 2 3.6 i ol = 100 m a ?0.3 0.4 mux out i ol = 2 ma ?0.3 0.7 i ol = 100 m a ?0.5 0.4 v ol non-muxed out v i ol = 2 ma ?0.5 0.7 i ol = 3 ma 0.4 sda i ol = 6 ma 0.6 scl, sda ?1.5 ?12 m a i ih override, mux select, wp v ih = 2.4 v ?20 ?100 mux in ?0.166 ?0.75 ma scl, sda ?7 ?32 m a i il override, mux select, wp v il = 0.4 v ?86 ?267 mux in ?0.72 ?2 ma during read or write cycle v i = 0 to v cc , i o = 0, v cc = 3.3 v 10 ma i cc not during read or write cycle v i = v cc , i o = 0 500 m a c i v i = v cc or gnd 10 pf (1) v hys is the hysteresis of schmitt-trigger inputs. parameter specifications write time (t wr ) 10 ms, typical memory-cell data retention 10 years, minimum maximum number of memory-cell write cycles 1000 cycles, minimum 4 www .ti.com
i 2 c interface timing requirements switching characteristics PCA8550 nonvolatile 5-bit register with i 2 c interface scps050c ? march 1999 ? revised may 2005 over recommended operating free-air temperature range (unless otherwise noted) (see figure 1 ) v cc = 3.3 v 0.3 v unit min max f scl i 2 c clock frequency 10 400 khz t sch i 2 c clock high time 600 ns t scl i 2 c clock low time 1.3 m s t sp i 2 c spike time 0 50 ns t sds i 2 c serial data setup time 100 ns t sdh i 2 c serial data hold time 0 900 ns t icr i 2 c input rise time 20 300 ns t icf i 2 c input fall time 20 300 ns t ocf i 2 c output fall time (10-pf to 400-pf bus) 20 + 0.1 c b (1) 250 ns t buf i 2 c bus free time between stop and start 1.3 m s t sts i 2 c start or repeated start condition setup 600 ns t sth i 2 c start or repeated start condition hold 600 ns t sps i 2 c stop condition setup 600 ns c b (1) i 2 c bus capacitive load 400 pf (1) c b = capacitance of one bus line in pf over recommended operating free-air temperature range (unless otherwise noted) (see figure 2 ) v cc = 3.3 v from to 0.3 v parameter unit (input) (output) min max t mpd mux input to output propagation delay mux in mux out 20 ns t sov mux select to output valid mux select output valid 22 ns t ovn override to non-muxed out output delay override non-muxed out 15 ns t ovm override to mux out output delay override mux out 25 ns falling edge of first valid data byte t su setup time wp 30 ns acknowledge on the scl input falling edge of first valid data byte t h hold time wp 120 ns acknowledge on the scl input t r output rise time 1 3 ns/v t f output fall time 1 3 ns/v 5 www .ti.com
parameter measurement information PCA8550 nonvolatile 5-bit register with i 2 c interface scps050c ? march 1999 ? revised may 2005 figure 1. i 2 c interface load circuit and voltage waveforms 6 www .ti.com dut r l = 1 k w v o = 3.3 v c l = 10 pf or c l = 400 pf gnd t b u f t i c r t s t h t s d s t s d h t i c f t i c r t s c l t s c h t s t s t p h l t p l h 0.7 v c c stop condition t s p s repeat start condition start orrepeat start condition scl sda start condition (s) bit 7 msb bit 6 bit 0 lsb (r/w ) acknowledge (a) stop condition (p) 2 bytes for complete device programming load circuit vol t age w a veforms t i c f stop condition (p) t s p t s u wp 2.7 v 0 v 1.5 v 1.5 v t h 0.3 v c c 0.7 v c c 0.3 v c c byte description 12 i 2 c address nonvolatile register data
parameter measurement information PCA8550 nonvolatile 5-bit register with i 2 c interface scps050c ? march 1999 ? revised may 2005 figure 2. load circuit and voltage waveforms 7 www .ti.com from output under t est c l = 15 pf (see note a) load circuit vol t age w a veforms prop aga tion dela y times for muxed out outputs t p l h t p h l 2.7 v0 v input output (see note e) notes: a. c l includes probe and jig capacitance. b. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.5 ns, t f 2.5 ns. c. the outputs are measured one at a time, with one transition per measurement. d. t p l h and t p h l are the same as t s o v and t o v n . e. t p l h and t p h l are the same as t m p d , t s o v , and t o v m . 1.5 v 1.5 v 1.25 v 1.25 v vol t age w a veforms prop aga tion dela y times for non-muxed out output t p l h t p h l 2.7 v0 v input output (see note d) 1.5 v 1.5 v 1.5 v 1.5 v v o h v o l v o h v o l
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) PCA8550d active soic d 16 tbd call ti call ti PCA8550dbr active ssop db 16 tbd call ti call ti PCA8550dbre4 active ssop db 16 tbd call ti call ti PCA8550de4 active soic d 16 tbd call ti call ti PCA8550dr active soic d 16 tbd call ti call ti PCA8550dre4 active soic d 16 tbd call ti call ti PCA8550pwr active tssop pw 16 tbd call ti call ti PCA8550pwre4 active tssop pw 16 tbd call ti call ti (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 26-dec-2005 addendum-page 1

mechanical data msso002e ? january 1995 ? revised december 2001 post office box 655303 ? dallas, texas 75265 db (r-pdso-g**) plastic small-outline 4040065 /e 12/01 28 pins shown gage plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 seating plane 9,90 7,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 a 28 1 20 16 6,50 6,50 14 0,05 min 5,90 5,90 dim a max a min pins ** 2,00 max 6,90 7,50 0,65 m 0,15 0 ? 8 0,10 0,09 0,25 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-150
mechanical data mtss001c january 1995 revised february 1999 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security low power wireless www.ti.com/lpw telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2006, texas instruments incorporated

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